Title | | Check model for block upgrade issues |
TitleID | | mathworks.design.Update |
|
Title | | Check rapid accelerator signal logging |
TitleID | | mathworks.design.CheckRapidAcceleratorSignalLogging |
|
Title | | Check get_param calls for block CompiledSampleTime |
TitleID | | mathworks.design.CallsGetParamCompiledSampleTime |
|
Title | | Identify unconnected lines, input ports, and output ports |
TitleID | | mathworks.design.UnconnectedLinesPorts |
|
Title | | Check root model Inport block specifications |
TitleID | | mathworks.design.RootInportSpec |
|
Title | | Identify blocks using one-based indexing |
TitleID | | mathworks.codegen.cgsl_0101 |
|
Title | | Check solver for code generation |
TitleID | | mathworks.codegen.SolverCodeGen |
|
Title | | Identify questionable blocks within the specified system |
TitleID | | mathworks.codegen.QuestionableBlks |
|
Title | | Check for blocks not supported by code generation |
TitleID | | mathworks.codegen.codeGenSupport |
|
Title | | Check for blocks not recommended for C/C++ production code deployment |
TitleID | | mathworks.codegen.PCGSupport |
|
Title | | Check for model reference configuration mismatch |
TitleID | | mathworks.codegen.MdlrefConfigMismatch |
|
Title | | Check diagnostic settings ignored during accelerated model reference simulation |
TitleID | | mathworks.design.ModelRefSIMConfigCompliance |
|
Title | | Check code generation identifier formats used for model reference |
TitleID | | mathworks.codegen.ModelRefRTWConfigCompliance |
|
Title | | Identify lookup table blocks that generate expensive out-of-range checking code |
TitleID | | mathworks.codegen.LUTRangeCheckCode |
|
Title | | Check output types of logic blocks |
TitleID | | mathworks.codegen.LogicBlockUseNonBooleanOutput |
|
Title | | Check the hardware implementation |
TitleID | | mathworks.codegen.HWImplementation |
|
Title | | Check optimization settings |
TitleID | | mathworks.design.OptimizationSettings |
|
Title | | Identify questionable software environment specifications |
TitleID | | mathworks.codegen.SWEnvironmentSpec |
|
Title | | Identify questionable code instrumentation (data I/O) |
TitleID | | mathworks.codegen.CodeInstrumentation |
|
Title | | Check for parameter tunability information ignored for referenced models |
TitleID | | mathworks.design.ParamTunabilityIgnored |
|
Title | | Check for implicit signal resolution |
TitleID | | mathworks.design.ImplicitSignalResolution |
|
Title | | Check for optimal bus virtuality |
TitleID | | mathworks.design.OptBusVirtuality |
|
Title | | Check for calls to slDataTypeAndScale() |
TitleID | | mathworks.design.CallslDataTypeAndScale |
|
Title | | Check for Discrete-Time Integrator blocks with initial condition uncertainty |
TitleID | | mathworks.design.DiscreteTimeIntegratorInitCondition |
|
Title | | Identify disabled library links |
TitleID | | mathworks.design.DisabledLibLinks |
|
Title | | Identify parameterized library links |
TitleID | | mathworks.design.ParameterizedLibLinks |
|
Title | | Identify unresolved library links |
TitleID | | mathworks.design.UnresolvedLibLinks |
|
Title | | Identify variant blocks that override variant choice |
TitleID | | mathworks.design.VariantOverride |
|
Title | | Identify configurable subsystem blocks for converting to variant subsystem blocks |
TitleID | | mathworks.design.CSStoVSSConvert |
|
Title | | Check usage of function-call connections |
TitleID | | mathworks.design.CheckForProperFcnCallUsage |
|
Title | | Check and update masked blocks in library to use promoted parameters |
TitleID | | mathworks.design.CheckAndUpdateOldMaskedBuiltinBlocks |
|
Title | | Check and update mask image display commands with unnecessary imread() function calls |
TitleID | | mathworks.design.CheckMaskDisplayImageFormat |
|
Title | | Check and update mask to affirm icon drawing commands dependency on mask workspace |
TitleID | | mathworks.design.CheckMaskRunInitFlag |
|
Title | | Check model configuration settings against code generation objectives |
TitleID | | mathworks.codegen.CodeGenSanity |
|
Title | | Check for efficiency optimization parameters |
TitleID | | mathworks.codegen.checkEnableMemcpy |
|
Title | | Identify library clones |
TitleID | | com.mathworks.Simulink.CloneDetection.LibraryClones |
|
Title | | Identify graphical clones |
TitleID | | com.mathworks.Simulink.CloneDetection.GraphicalClones |
|
Title | | Identify similar library clones |
TitleID | | com.mathworks.Simulink.CloneDetection.IdentifyStructLibraryClones |
|
Title | | Identify similar graphical clones |
TitleID | | com.mathworks.Simulink.CloneDetection.IdentifyStructGraphicalClones |
|
Title | | Check and update model to use toolchain approach to build generated code |
TitleID | | mathworks.codegen.toolchainInfoUpgradeAdvisor.check |
|
Title | | Check and set embedded target model to use ert.tlc system target file |
TitleID | | mathworks.codegen.codertarget.check |
|
Title | | Check model simulation configuration |
TitleID | | mathworks.fpa.CheckModelSimulationConfiguration |
|
Title | | Check model Diagnostics Data Validity settings |
TitleID | | mathworks.fpa.CheckDataValidityDiagnosticsForParameters |
|
Title | | Simulation range checking |
TitleID | | mathworks.fpa.CheckSimulationRangeChecking |
|
Title | | Verify explicit signal resolution |
TitleID | | mathworks.fpa.CheckImplicitSignalResolution |
|
Title | | Check strong data typing with Simulink I/O |
TitleID | | mathworks.fpa.CheckStrongDataTypingWithSimulinkIO |
|
Title | | Address unsupported blocks |
TitleID | | mathworks.fpa.CheckUnsupportedBlocks |
|
Title | | Specify block minimum and maximum values |
TitleID | | mathworks.fpa.CheckSpecifyDesignMinMaxValue |
|
Title | | Review locked data type settings |
TitleID | | mathworks.fpa.CheckSummarizeLockDownKnownScaling |
|
Title | | Return to Fixed-Point Tool to Perform Data Typing and Scaling |
TitleID | | mathworks.fpa.launchFPT |
|
Title | | Identify system constants for use in variant transformation |
TitleID | | com.mathworks.Simulink.MdlTransformer.IdentifyVariantConstant |
|
Title | | Identify blocks that qualify for variant transformation |
TitleID | | com.mathworks.Simulink.MdlTransformer.IdentifyVariantCandidate |
|
Title | | Convert blocks to variants |
TitleID | | com.mathworks.Simulink.MdlTransformer.VariantTransform |
|
Title | | Check for Saturate on Integer Overflow setting in MATLAB Function Blocks |
TitleID | | com.mathworks.HDL.ModelChecker.runMLFcnBlkSatIntChecks |
|
Title | | Check for Fimath setting in MATLAB Function Blocks |
TitleID | | com.mathworks.HDL.ModelChecker.runMLFcnBlkFimathChecks |
|
Title | | Check Stateflow chart settings |
TitleID | | com.mathworks.HDL.ModelChecker.runStateflowChartSettingsChecks |
|
Title | | Check for atomic Stateflow sub-charts |
TitleID | | com.mathworks.HDL.ModelChecker.runStateflowAtomicSubchartChecks |
|
Title | | Check for sample times |
TitleID | | com.mathworks.HDL.ModelChecker.runSampleTimeChecks |
|
Title | | Check for safe model parameters |
TitleID | | com.mathworks.HDL.ModelChecker.runModelParamsChecks |
|
Title | | Check for global reset setting for Xilinx and Altera devices |
TitleID | | com.mathworks.HDL.ModelChecker.runGlobalResetChecks |
|
Title | | Check for blocks not supported with Native Floating Point setting |
TitleID | | com.mathworks.HDL.ModelChecker.runNFPSupportedBlocksChecks |
|
Title | | Check for operations not supported with Math and Trigonometry Function blocks |
TitleID | | com.mathworks.HDL.ModelChecker.runNFPSupportedOperatorsChecks |
|
Title | | Display blocks that have non-zero output latency |
TitleID | | com.mathworks.HDL.ModelChecker.runNFPLatencyChecks |
|
Title | | Display blocks that have non-zero ULP Error |
TitleID | | com.mathworks.HDL.ModelChecker.runNFPULPErrorChecks |
|
Title | | Check for invalid DUT |
TitleID | | com.mathworks.HDL.ModelChecker.runInvalidDUTChecks |
|
Title | | Check initial conditions for enabled/triggered subsystems |
TitleID | | com.mathworks.HDL.ModelChecker.runEnTrigInitConChecks |
|
Title | | Create baseline to measure the performance. The baseline contains the time to run the simulation and the simulation results (signals logged). To create a baseline, configure the model to log states in the workspace and save the signals in 'Structure with time' format. |
TitleID | | com.mathworks.Simulink.PerformanceAdvisor.CreateBaseline |
|
Title | | Some diagnostics, such as 'Solver data inconsistency', incur run-time overhead during simulation. To improve simulation speed, disable these diagnostics if they are not necessary. |
TitleID | | com.mathworks.Simulink.PerformanceAdvisor.IdentifyExpensiveDiagnostics |
|
Title | | Some optimizations, such as 'Block reduction', may be disabled. To improve simulation speed, enable these optimization settings. |
TitleID | | com.mathworks.Simulink.PerformanceAdvisor.IdentifyApplicableOptimizations |
|
Title | | Improperly configured lookup table blocks can affect the simulation speed of a model. |
TitleID | | com.mathworks.Simulink.PerformanceAdvisor.InefficientLookupTableBlocks |
|
Title | | Analyze MATLAB System block for code generation capability. |
TitleID | | com.mathworks.Simulink.PerformanceAdvisor.DetectIntSysObjBlocks |
|
Title | | Avoid using Interpreted MATLAB Function blocks. |
TitleID | | com.mathworks.Simulink.PerformanceAdvisor.DetectIntMATLABFcnBlocks |
|
Title | | Disabling simulation target settings, such as 'Echo expressions without semicolons', can improve simulation speed. |
TitleID | | com.mathworks.Simulink.PerformanceAdvisor.CheckSimTargetEchoStatus |
|
Title | | Check if model reference rebuild setting is set to the proper value |
TitleID | | com.mathworks.Simulink.PerformanceAdvisor.CheckModelRefRebuildSetting |
|
Title | | Opened and uncommented Scopes can impact simulation performance. This check identifies Scope block, Floating Scope block, and Scope Viewer. Scope Viewer does not support commenting out. |
TitleID | | com.mathworks.Simulink.PerformanceAdvisor.IdentifyScopes |
|
Title | | Identify active instrumentation settings on the model. This setting can cause slow simulations due to range collection. |
TitleID | | com.mathworks.Simulink.PerformanceAdvisor.IdentifyActiveMMO |
|
Title | | System Target File Compatibility |
TitleID | | com.mathworks.Simulink.AdvisorRealTime.SystemTargetFile |
|
Title | | Profiling Settings |
TitleID | | com.mathworks.Simulink.AdvisorRealTime.ProfilingSettings |
|
Title | | Check Target |
TitleID | | com.mathworks.Simulink.AdvisorRealTime.CheckTarget |
|
Title | | Outport Logging |
TitleID | | com.mathworks.Simulink.AdvisorRealTime.OutportLogging |
|
Title | | EtherCAT Synchronous SDO |
TitleID | | com.mathworks.Simulink.AdvisorRealTime.EtherCAT_Sync_SDO |
|
Title | | Check model and local libraries for SB2SL blocks |
TitleID | | mathworks.simulink.SB2SL.Check |
|
Title | | Runtime diagnostics for S-functions |
TitleID | | mathworks.design.DiagnosticSFcn |
|
Title | | Check if Read/Write diagnostics are enabled for Data Store blocks |
TitleID | | mathworks.design.DiagnosticDataStoreBlk |
|
Title | | Check Data Store Memory blocks for multitasking, strong typing, and shadowing issues |
TitleID | | mathworks.design.DataStoreMemoryBlkIssue |
|
Title | | Check that the model is saved in SLX format |
TitleID | | mathworks.design.UseSLXFile |
|
Title | | Check model for foreign characters |
TitleID | | mathworks.design.characterEncoding |
|
Title | | Check Model History properties |
TitleID | | mathworks.design.SLXModelProperties |
|
Title | | Identify masked blocks that specify tabs in mask dialog using MaskTabNames parameter |
TitleID | | mathworks.design.CheckAndUpdateOldMaskTabnames |
|
Title | | Check conversion input parameters |
TitleID | | com.mathworks.Simulink.ModelReferenceAdvisor.InputParameters |
|
Title | | Check model configurations |
TitleID | | com.mathworks.Simulink.ModelReferenceAdvisor.ModelConfigurations |
|
Title | | Check subsystem interface |
TitleID | | com.mathworks.Simulink.ModelReferenceAdvisor.SubsystemInterface |
|
Title | | Check subsystem content |
TitleID | | com.mathworks.Simulink.ModelReferenceAdvisor.SubsystemContent |
|
Title | | Complete conversion |
TitleID | | com.mathworks.Simulink.ModelReferenceAdvisor.CompleteConversion |
|
Title | | Identify Model Info blocks that use the Configuration Manager |
TitleID | | mathworks.design.ModelInfoConfigurationManager |
|
Title | | Identify Model Info blocks that can interact with external source control tools |
TitleID | | mathworks.design.ModelInfoKeywordSubstitution |
|
Title | | Open the Upgrade Advisor |
TitleID | | com.mathworks.Simulink.UpgradeAdvisor.MAEntryPoint |
|
Title | | Upgrade models in a hierarchy |
TitleID | | com.mathworks.Simulink.UpgradeAdvisor.UpgradeModelHierarchy |
|
Title | | Set Target Frequency |
TitleID | | com.mathworks.HDL.SetGenericTargetFrequency |
|
Title | | Set Target Frequency |
TitleID | | com.mathworks.HDL.SetTargetFrequency |
|
Title | | Check model-level settings for HDL code generation |
TitleID | | com.mathworks.HDL.CheckGlobalSettings |
|
Title | | Set basic options for RTL code generation |
TitleID | | com.mathworks.HDL.SetBasicOptions |
|
Title | | Set advanced options |
TitleID | | com.mathworks.HDL.SetAdvancedOptions |
|
Title | | Set Optimization Options |
TitleID | | com.mathworks.HDL.SetOptimizationOptions |
|
Title | | Set testbench options |
TitleID | | com.mathworks.HDL.SetTBOptions |
|
Title | | Verify generated RTL code with a HDL Cosimulation testbench |
TitleID | | com.mathworks.HDL.VerifyCosim |
|
Title | | Create synthesis tool project |
TitleID | | com.mathworks.HDL.CreateProject |
|
Title | | Run logic synthesis for specified FPGA device |
TitleID | | com.mathworks.HDL.RunLogicSynthesis |
|
Title | | Run mapping for specified FPGA device |
TitleID | | com.mathworks.HDL.RunMapping |
|
Title | | Run place and route for specified FPGA device |
TitleID | | com.mathworks.HDL.RunPandR |
|
Title | | Run logic synthesis for specified FPGA device |
TitleID | | com.mathworks.HDL.RunVivadoSynthesis |
|
Title | | Run place and route for specified FPGA device |
TitleID | | com.mathworks.HDL.RunImplementation |
|
Title | | Annotate synthesis result back to the Simulink model |
TitleID | | com.mathworks.HDL.AnnotateModel |
|
Title | | Generate programming file for specified FPGA device |
TitleID | | com.mathworks.HDL.GenerateBitstream |
|
Title | | Program target FPGA device |
TitleID | | com.mathworks.HDL.ProgramDevice |
|
Title | | Generate Simulink Real-Time interface |
TitleID | | com.mathworks.HDL.GeneratexPCInterface |
|
Title | | Set FPGA-in-the-Loop Options |
TitleID | | com.mathworks.HDL.FILOption |
|
Title | | Generate FPGA programming file and FPGA-in-the-Loop testbench model |
TitleID | | com.mathworks.HDL.RunFIL |
|
Title | | Generate FPGA programming file for USRP(R) board. The FPGA project is generated first. Then syntax checking is performed on the HDL code. If no error was found in FPGA project generation and syntax checking, FPGA programming file generation process will start in an external command-line window. |
TitleID | | com.mathworks.HDL.RunUSRP |
|
Title | | Create project for embedded system tool |
TitleID | | com.mathworks.HDL.EmbeddedProject |
|
Title | | Generate a software interface model with IP core driver blocks for C code generation. |
TitleID | | com.mathworks.HDL.EmbeddedModelGen |
|
Title | | Generate a software interface model with IP core driver blocks. |
TitleID | | com.mathworks.HDL.EmbeddedCustomModelGen |
|
Title | | Synthesis and generate bitstream for embedded system on FPGA |
TitleID | | com.mathworks.HDL.EmbeddedSystemBuild |
|
Title | | Program target FPGA device |
TitleID | | com.mathworks.HDL.EmbeddedDownload |
|
Title | | Check configuration parameters for MISRA C:2012 |
TitleID | | mathworks.misra.CodeGenSettings |
|
Title | | Check for blocks not recommended for MISRA C:2012 |
TitleID | | mathworks.misra.BlkSupport |
|
Title | | Check for unsupported block names |
TitleID | | mathworks.misra.BlockNames |
|
Title | | Check usage of Assignment blocks |
TitleID | | mathworks.misra.AssignmentBlocks |
|
Title | | Check for virtual bus across model reference boundaries |
TitleID | | mathworks.design.CheckVirtualBusAcrossModelReference |
|
Title | | Check model for parameter initialization and tuning issues |
TitleID | | mathworks.design.ParameterTuning |
|
Title | | Check structure parameter usage with bus signals |
TitleID | | mathworks.design.MismatchedBusParams |
|
Title | | Identify questionable subsystem settings |
TitleID | | mathworks.codegen.QuestionableSubsysSetting |
|
Title | | Identify functional clones |
TitleID | | com.mathworks.Simulink.CloneDetection.FunctionalClones |
|
Title | | Identify similar functional clones |
TitleID | | com.mathworks.Simulink.CloneDetection.IdentifyStructFunctionalClones |
|
Title | | Check update diagram status |
TitleID | | mathworks.fpa.CheckUpdateDiagramStatus |
|
Title | | Set up signal logging |
TitleID | | mathworks.fpa.CheckSetupSignalLogging |
|
Title | | Create reference data |
TitleID | | mathworks.fpa.CheckCreateReferenceData |
|
Title | | Implement logic signals as Boolean data |
TitleID | | mathworks.fpa.CheckImplementLogicSignalsAsBooleanData |
|
Title | | Check for removing redundant specification between signal objects and blocks |
TitleID | | mathworks.fpa.CheckAssociateSDOWithBlocks |
|
Title | | Relax input data type settings |
TitleID | | mathworks.fpa.CheckRelaxInputDatatypeSettings |
|
Title | | Check if model with referenced models can be built in parallel with optimal settings. |
TitleID | | com.mathworks.Simulink.PerformanceAdvisor.CheckModelRefParallelBuild |
|
Title | | Use circular buffer to improve simulation speed for Delay blocks with large states. |
TitleID | | com.mathworks.Simulink.PerformanceAdvisor.CheckDelayBlockCircularBufferSetting |
|
Title | | Simulation might slow down if all these conditions exist: (1) the model is using a variable step solver, (2) the model contains both continuous and discrete rates, and (3) the fastest discrete rate is relatively smaller than 'Max step size' determined by the solver. Setting 'DecoupleContODEIntegFromDiscRates' parameter to 'on' might speed up simulation. |
TitleID | | com.mathworks.Simulink.PerformanceAdvisor.CheckIfNeedDecoupleContDiscRates |
|
Title | | Check discrete signals driving derivative port |
TitleID | | com.mathworks.Simulink.PerformanceAdvisor.CheckDiscDriveContSignal |
|
Title | | The selection of an explicit or implicit solver depends on the approximation of the model stiffness at the beginning of the simulation. If the model represents a stiff system, use the ode15s solver. Otherwise, use the ode45 solver. |
TitleID | | com.mathworks.Simulink.PerformanceAdvisor.SolverTypeSelection |
|
Title | | Changing simulation mode can improve simulation speed. |
TitleID | | com.mathworks.Simulink.PerformanceAdvisor.CheckSimulationModesComparison |
|
Title | | Running with compiler optimizations turned on can improve simulation speed. |
TitleID | | com.mathworks.Simulink.PerformanceAdvisor.CheckSimulationCompilerOptimization |
|
Title | | Validate the overall performance improvement in your model using this check. If performance is worse than baseline, Performance Advisor discards all changes and loads the original model. |
TitleID | | com.mathworks.Simulink.PerformanceAdvisor.FinalValidation |
|
Title | | Real-Time Performance Baseline |
TitleID | | com.mathworks.Simulink.AdvisorRealTime.RealTimeBaseline |
|
Title | | Concurrent execution |
TitleID | | com.mathworks.Simulink.AdvisorRealTime.ConcurrentCapable |
|
Title | | Determine minimum sample time |
TitleID | | com.mathworks.Simulink.AdvisorRealTime.MinSampleTime |
|
Title | | Final validation |
TitleID | | com.mathworks.Simulink.AdvisorRealTime.FinalValidation |
|
Title | | Set Target Device and Synthesis Tool for HDL code generation |
TitleID | | com.mathworks.HDL.SetTargetDevice |
|
Title | | Set target reference design options |
TitleID | | com.mathworks.HDL.SetTargetReferenceDesign |
|
Title | | Set target interface for HDL code generation |
TitleID | | com.mathworks.HDL.SetTargetInterface |
|
Title | | Set target interface for HDL code generation |
TitleID | | com.mathworks.HDL.SetTargetInterfaceAndMode |
|
Title | | Check model for algebraic loops |
TitleID | | com.mathworks.HDL.CheckAlgebraicLoop |
|
Title | | Check model for unsupported blocks |
TitleID | | com.mathworks.HDL.CheckBlockCompatibility |
|
Title | | Check model for global sample time settings |
TitleID | | com.mathworks.HDL.CheckSampleTime |
|
Title | | Check model compatibility with FPGA-in-the-Loop |
TitleID | | com.mathworks.HDL.CheckFIL |
|
Title | | Check model compatibility with USRP(R) workflow |
TitleID | | com.mathworks.HDL.CheckUSRP |
|
Title | | Generate RTL code and testbench for the selected subsystem |
TitleID | | com.mathworks.HDL.GenerateHDLCodeAndReport |
|
Title | | Generate RTL code and IP core for embedded system |
TitleID | | com.mathworks.HDL.GenerateIPCore |
|
Title | | Generate RTL code and top level wrapper for the selected subsystem |
TitleID | | com.mathworks.HDL.GenerateRTLCode |
|
Title | | Check model for block upgrade issues requiring compile time information |
TitleID | | mathworks.design.UpdateRequireCompile |
|
Title | | Check sample times and tasking mode |
TitleID | | mathworks.codegen.SampleTimesTaskingMode |
|
Title | | Check for blocks that have constraints on tunable parameters |
TitleID | | mathworks.codegen.ConstraintsTunableParam |
|
Title | | Check Delay, Unit Delay and Zero-Order Hold blocks for rate transition |
TitleID | | mathworks.design.ReplaceZOHDelayByRTB |
|
Title | | Check bus signals treated as vectors |
TitleID | | mathworks.design.BusTreatedAsVector |
|
Title | | Check for potentially delayed function-call block return values |
TitleID | | mathworks.design.DelayedFcnCallSubsys |
|
Title | | Identify block output signals with continuous sample time and non-floating point data type |
TitleID | | mathworks.design.OutputSignalSampleTime |
|
Title | | Check usage of Merge blocks |
TitleID | | mathworks.design.MergeBlkUsage |
|
Title | | Check usage of Outport blocks |
TitleID | | mathworks.design.InitParamOutportMergeBlk |
|
Title | | Check usage of Discrete-Time Integrator blocks |
TitleID | | mathworks.design.DiscreteBlock |
|
Title | | Check model settings for migration to simplified initialization mode |
TitleID | | mathworks.design.ModelLevelMessages |
|
Title | | Check model for custom library blocks that rely on frame status of the signal |
TitleID | | mathworks.design.DSPFrameUpgrade |
|
Title | | Identify blocks that generate expensive fixed-point and saturation code |
TitleID | | mathworks.codegen.BlockSpecificQuestionableFxptOperations |
|
Title | | Check for single datatypes in the model |
TitleID | | com.mathworks.HDL.ModelChecker.runNFPSuggestionChecks |
|
Title | | Check for double datatypes in the model |
TitleID | | com.mathworks.HDL.ModelChecker.runDoubleDatatypeChecks |
|
Title | | Check for non-continuous signals driving derivative ports |
TitleID | | mathworks.design.NonContSigDerivPort |
|
Title | | Check data store block sample times for modeling errors |
TitleID | | mathworks.design.DataStoreBlkSampleTime |
|
Title | | Check for potential ordering issues involving data store access |
TitleID | | mathworks.design.OrderingDataStoreAccess |
|
Title | | Check virtual bus inputs to blocks |
TitleID | | mathworks.design.VirtualBusUsage |
|
Title | | Check for root outports with constant sample time |
TitleID | | mathworks.design.CheckConstRootOutportWithInterfaceUpgrade |
|
Title | | Identify unit mismatches in the model |
TitleID | | mathworks.design.UnitMismatches |
|
Title | | Identify automatic unit conversions in the model |
TitleID | | mathworks.design.AutoUnitConversions |
|
Title | | Identify disallowed unit systems in the model |
TitleID | | mathworks.design.DisallowedUnitSystems |
|
Title | | Identify undefined units in the model |
TitleID | | mathworks.design.UndefinedUnits |
|
Title | | Check for switch case expressions without a default case |
TitleID | | mathworks.misra.SwitchDefault |
|
Title | | Identify time-varying source blocks interfering with frequency response estimation |
TitleID | | mathworks.slcontrolfrest.timevaryingsources |
|
Title | | Identify questionable fixed-point operations |
TitleID | | mathworks.codegen.QuestionableFxptOperations |
|
Title | | Identify blocks that generate expensive rounding code |
TitleID | | mathworks.codegen.ExpensiveSaturationRoundingCode |
|
Title | | Identify questionable operations for strict single-precision design |
TitleID | | mathworks.design.StowawayDoubles |
|
Title | | Check for bitwise operations on signed integers |
TitleID | | mathworks.misra.CompliantCGIRConstructions |
|
Title | | Check for recursive function calls |
TitleID | | mathworks.misra.RecursionCompliance |
|
Title | | Check for equality and inequality operations on floating-point values |
TitleID | | mathworks.misra.CompareFloatEquality |
|
| |
Task Name | | Modeling Signals and Parameters using Buses |
|
Task Name | | Code Generation Efficiency |
|
Task Name | | Modeling Single-Precision Systems |
|
Task Name | | Migrating to Simplified Initialization mode |
|
Task Name | | Model Referencing |
|
Task Name | | Managing Library Links And Variants |
|
Task Name | | Data Transfer Efficiency |
|
Task Name | | Simulation Accuracy |
|
Task Name | | Simulation Runtime Accuracy Diagnostics |
|
Task Name | | Managing Data Store Memory Blocks |
|
Task Name | | Simulink Model File Integrity |
|
Task Name | | Units Inconsistencies |
|
Task Name | | Upgrading to the Current Simulink Version |
|
Task Name | | Modeling Guidelines for MISRA C:2012 |
|
Task Name | | Frequency Response Estimation |
|